1. Field of the Invention
This invention relates to a semiconductor device, and in particular to a dual-gate complementary MOS field-effect transistor (CMOSFET), and to a method of manufacturing same.
2. Description of Related Art
A complementary MOSFET, fabricated from an n-channel MOS field-effect transistor (nMOSFET) and a p-channel MOS field-effect transistor (pMOSFET), has attracted attention as an integrated circuit enabling operation under a low consumption current and high-speed operation.
A layered structure (polyside structure), in which for example polycrystalline silicon layers and metal silicide (WSix or similar) layers are stacked on a gate insulating layer, is widely adopted in each of the gate electrodes of a CMOSFET. Here W represents a metal element, and x indicates the composition ratio. In particular, a dual-gate CMOSFET, in which are provided an n+ gate electrode in which n type impurities (an n dopant) are implanted in a polysilicon layer on the nMOSFET side and a p+ gate electrode in which p type impurities (a p dopant) are implanted in the polysilicon layer on the pMOSFET side, has a structure which is effective for suppressing the short-channel effect.
Each of the gate electrodes of a dual-gate CMOSFET is formed by patterning a common layered structure into a gate electrode shape. This common layered structure is formed by, for example, stacking a metal silicide layer on top of a polycrystalline silicon layer. This polycrystalline silicon layer is provided on top of a substrate, and has two impurity diffusion regions, in which n type and p type impurities are respectively diffused.
However, in the process to manufacture a dual-gate CMOSFET, after forming the common layered structure, the common layered structure is heat-treated at high temperatures.
As a result, when for example activating the impurities which have been implanted in the polycrystalline silicon layers of each gate electrode after formation of the metal silicide layer, due to the high-temperature heat treatment of the metal silicide layer, the n type and p type impurities which are diffused in the polycrystalline silicon layer undergo interdiffusion through the metal silicide layer. As a result of this interdiffusion, the n type and p type impurities compensate each other.
Hence in gate electrodes formed from a layered structure in which compensation occurs due to interdiffusion, the threshold voltage Vth fluctuates due to enlargement of the depletion layer when a voltage is applied, so that the CMOSFET characteristics are degraded.
In order to suppress the degradation of CMOSFET characteristics, a method has been proposed in which the CMOSFET is configured with sufficient distance provided between the nMOSFET and pMOSFET, by broadening the portion in which the device isolation film exists or by similar means. However, this method is not well-suited to finer device patterns and higher integration densities.
Another method, in which the heat-treatment temperature in the heat-treatment process is suppressed, has also been proposed. However, as a result of suppression of the heat-treatment temperature, activation of the implanted impurities is insufficient, and consequently the contact resistance is increased and recovery of lattice defects is inadequate. That is, when this method is used, the performance and reliability of the device are worsened.
Thus one object of this invention is to provide a semiconductor device and manufacturing method in which interdiffusion of n type and p type impurities diffused in a polycrystalline silicon layer is suppressed.
A semiconductor device manufacturing method of this invention has the following features with regard to configuration.
The manufacturing method, used to manufacture a semiconductor device comprising a first gate electrode and a second gate electrode provided at a distance from the first gate electrode, comprises the following processes (a) through (e). However, the first gate electrode has a first impurity diffusion layer with a first conduction type formed on a polycrystallinei silicon layer and a high-melting-point metal layer or high-melting-point metal silicide layer, formed in sequence. Also, the second gate electrode has a second impurity diffusion layer with a second conduction type formed on a polycrystalline silicon layer and a high-melting-point metal layer or high-melting-point metal silicide layer, formed in sequence.
(a) First and second conduction type impurities are respectively implanted into mutually different first and second regions in a polycrystalline silicon layer, from above the polycrystalline layer. (Impurity implantation process)
(b) After the impurity implantation process, an impurity thermal diffusion prevention layer is formed on the polycrystalline silicon layer. This impurity thermal diffusion prevention layer acts to prevent the diffusion of impurities implanted into the polycrystalline silicon layer. (Impurity thermal diffusion prevention layer formation process)
(c) A high-melting-point metal layer or high-melting-point metal silicide layer is formed so as to cover the polycrystalline silicon layer in which the first region and second region exist. A compound layer is formed comprising the polycrystalline silicon layer, in which are implanted impurities of the first and second conduction types; an impurity thermal diffusion prevention layer; and a high-melting-point metal layer or high-melting-point metal silicide layer. (Compound layer formation process)
(d) Heat treatment of the compound layer is performed. The first and second impurities, implanted in the first and second regions, are diffused in the polycrystalline silicon layer. First and second impurity diffusion layers are formed. (Diffusion layer formation process)
(e) The layers comprising the above polycrystalline silicon layer, in which are formed the above first and second impurity diffusion layers, the above impurity thermal diffusion prevention layer, and the above high-melting-point metal layer or high-melting-point metal silicide layer is patterned. The above first and second gate electrodes are formed. (Electrode formation process)
According to the method of manufacture of a semiconductor device of this invention, an impurity thermal diffusion prevention layer provided on top of a polycrystalline silicon layer can be made to function as a stopper layer to suppress the interdiffusion of impurities during high-temperature heat treatment.
Hence the occurrence of fluctuations in the threshold voltage Vth can be suppressed, accompanying suppression of the interdiffusion of impurities, so that semiconductor devices with high reliability, and compatible with high integration densities, can be obtained.